1. Technical Field
The present invention relates to a semiconductor memory device and, particularly, to a method and an apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. More particularly, the present invention relates to a method and an apparatus for performing read and write operations in an order such that write and read operations can be performed in cells associated with the same bit line.
2. Description of Related Art
As a consequence of a continued demand for systems providing high-speed operation and low electric power consumption, semiconductor memory devices are continually being developed that are suitable for enabling high-speed operation and the low electric power consumption. In a semiconductor memory device, a synchronous static random access memory device (SSRAM) performs read/write operations in response to an external clock signal. To obtain high-speed operation of a synchronous semiconductor memory device, a double data rate (DDR) mode is typically utilized in which dual clock is generated thereby doubling the clock speed (as compared with a single data rate mode (SDR)).
Typically, SDR and DDR semiconductor memory devices comprise an I/O structure comprising a common data input bus and data output bus. Since the data input bus and the data output bus cannot be operated at the same time, however, the data rate will be lowered when read and write commands are input at the same time in the same cycle. If a semiconductor memory device comprises an input/output structure in which the data input bus and data output bus are separated, the device can realize a substantial increase in the data rate in the same cycle time because the data input bus and the data output bus can simultaneously be operated.
It is an object of the present invention to provide a semiconductor device comprising an I/O architecture comprising a separate data input bus and data output bus.
It is another object of this invention to provide a method and an apparatus for simultaneously utilizing a data input bus and a data output bus in a separate input/output DDR or quadruple data rate RAM, whereby a semiconductor memory device can realize a data rate more than two times in a same cycle time and sequentially perform read and write operations in the same cycle.
It is another object of the present invention to provide a method and an apparatus for read and write operation in a semiconductor memory device by which read and write operations are sequentially performed in a same cycle when read and write operations are performed in a separate I/O DDR or QDR (2/4) RAM, thereby minimizing the cycle time.
In one aspect of the present invention, a method for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and a data output bus, comprises the steps of:
performing a read operation in synchronization with a clock signal when a read command is input at one cycle; and
performing a write operation in synchronization with a signal that operates during the read operation.
The signal that operates during the read operation may comprises a decoding signal, a main data line signal, or a sense amplifier enable signal that is enabled during the read operation.
In another aspect, a method for performing read and write operations further comprises performing a write operation in synchronization with the clock that is synchronized during a read operation if the read command is not input in the one cycle.
In yet another aspect, the cycle time in the one cycle is determined by the sum of a minimum cycle time for a read operation and a minimum cycle time for a write operation.
In another aspect, the I/O operates at a 4-bit burst double data rate using one of a 2 and 4-bit prefetch mode.
According to yet another aspect of the present invention, a method for performing read and write operations in a semiconductor memory device comprising an I/O architecture comprising a separate data input bus and data output bus, comprises the steps of:
performing a write operation in synchronization with a clock when a write command is input at one cycle; and
performing a read operation in synchronization with a signal that operates during the write operation.
The signal that operates during the write operation may comprise a decoding signal that is enabled during the write operation, a write driver enable signal, or a write driver disable signal.
According to yet another aspect, the method for performing read and write operations further comprises performing a read operation in synchronization with the clock that is synchronized during a write operation if the write command is not input in the one cycle.
In another aspect, the cycle time in the one cycle is determined by the sum of a minimum cycle time for a write operation and a minimum cycle time for a read operation.
In yet another aspect, the I/O operates at a 4-bit burst double data rate using one of a 2 and 4 bit prefetch mode.
In another aspect, in the write operation, when data is input earlier than a write address, a write operation is performed in a following write cycle.
In yet another aspect of the present invention, an apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus comprises:
an address register for latching an a read address or a write address;
a clock buffer for receiving clock signals;
a decoder for decoding a read or write address that is latched by the address register;
a memory cell array for enabling word lines and row paths in response to an address decoding signal received from the decoder;
a sense amplifier that is enabled for a read operation when a word line and a row path are enabled;
a write driver that is enabled for a write operation to write data in a cell when a word line and a row path are enabled;
a data output register for latching output data and outputting the output data in synchronization with a clock in a following cycle after the sense amplifier is enabled;
a data input register; and
a controller for tracking a random signal that operates during an earlier read or write operation to thereby perform a subsequent write or read operation.